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Ordering number:ENN3122A
CMOS IC
LC66P308
4-bit Microcontroller with Built-in PROM
Overview
The LC66P308 is a 4-bit microcontroller with a built-in 8 Kbyte PROM. It is compatible with the LC663XX series mask ROM devices, making it ideal for prototyping and software development and testing. The LC66P308 features 33 user-defined options comprising output configuration, output level after reset, watchdog timer and oscillator configuration options. The output configuration options are open-drain, open-drain with pullup, and CMOS. The oscillator options are ceramic resonator, RC oscillator and external clock. The LC66P308 operates from a 5 V supply and is available in 42-pin DIPs and 48-pin QIPs.
Package Dimensions
Unit:mm 3025B-DIP42S
[LC66P308]
42 22
15.24 13.8
1 37.9
21
0.51min 4.25 3.8 5.1max
Features
* 33 user-defined options including port output configuration, output level after reset and watchdog timer options * Ceramic resonator, RC oscillator or external clock option * 8 Kbyte PRQM (0000H to 2007H user addressable) * Compatible with the LC663XX series mask ROM devices * 0.92 to 10.0 s instruction cycle time * 5 V supply * 42-pin DIP and 48-pin QIP
0.95
0.48
1.78
1.15
SANYO : DIP42S
Unit:mm 3156-QIP48E
[LC66P308]
17.2 14.0 1.5
1.6
1.6 1.5 25 24 0.15
1.0
0.35
36
1.5
37
17.2
14.0
1.0
1.5
48 1 12
13
3.0max
0.1 2.7
0.8
15.6
SANYO : QIP48E
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
62001TN (KT)/6082JN (US)/8089TA No.3122-1/15
0.25
LC66P308
Pin Assignment
Top view
Block Diagram
No.3122-2/15
LC66P308
Pin Description
Number DIP42S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 24 25 19 20 21 22 23 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 - DIP48E 44 45 46 47 48 1 2 3 4 5 7 8 9 10 11 12 13 14 22 23 15 16 17 20 21 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 40 41 6, 18, 19, 30, 42, 43 Name D0/P00 D1/P01 D2/P02 D3/P03 D4/P10 D5/P11 D6/P12 D7/P13 A0/SI0/P20 A1/SO0/P21 A2/SCK0/P22 A3/INT0/P23 A4/INT1/P30 A5/POUT0/P31 A6/ROUT1/P32 HOLD/P33 A7/P40 A8/P41 A9/P42 A10/P43 VPP/TEST VSS OSC1 OSC2 RES A11/P50 A12/P51 A13/P52 INT2/P53 SI1/P60 SO1/P61 SCK1/P62 DASEC/PIN1/P63 PC2/VREF0 PC3/VREF1 PD0/CMP0 PD1/CMP1 PD2/CMP2 PD3/CMP3/PGM VDD PE0/TRA/CE PE1/TRB/OE NC 5V supply Multiplexed 2-bit input port PE (PE0 and PE1), 2-bit three-level input port (TRA and TRB), PROM chip enable (CE) and output enable (OE) No connection Multiplexed 4-bit input port PD (PD0 to PD3), PROM program control input (PGM) and comparator inputs (CMP0 to CMP3) Multiplexed 2-bit input/output port PC (PC2 and PC3), CMP0 reference voltage input (VREF0) and CMP1 to CMP3 reference voltage input (VREF1) Multiplexed 4-bit input/output port P6 (P60 to P63), serial input 1 (SI1), serial output 1 (SO1), serial clock 1 (SCK1), event counter input (PIN1) and PROM data security control input (DASEC) Multiplexed 4-bit input/output port P5 (P50 to P53), interrupt request 2 (INT2) and PROM address bus lines (A11 to A13) CPU test input Ground External oscillator connections Reset input Multiplexed 4-bit input/output port P4 (P40 to P43) and PROM address bus lines (A7 to A10) Multiplexed 3-bit input/output port P3 (P30 to P32), interrupt request 1 (INT1), timer outputs (POUT0 and POUT1) and address bus lines (A4 to A6) multiplexed singlebit input port (P33) and hold-mode control input (HOLD) Multiplexed 4-bit input/output port P2 (P20 to P23), serial input 0 (SI0), serial output 0 (SO0), serial clock 0 (SCK0), interrupt request 0 (INT0) and PROM address bus lines (A0 to A3) Multiplexed 4-bit input/output port P1 (P10 to P13) and PROM data bus lines (D4 to D7) Multiplexed 4-bit input/output port P0 (P00 to P03) and PROM data bus lines (D0 to D3) Description
No.3122-3/15
LC66P308 Specifications
Absolute Maximum Ratings at Ta =25C, VSS=0V
Parameter Supply voltage Ports P2 to P6 (excluding P33) input voltage Input voltage range for all inputs Ports P2 to P6 (excluding P33) output voltage Output voltage range for all outputs Ports P0, P1, P4 and P5 output source current Ports P2, P3 (excluding P33), P6 and PC output source current Ports P0 to P6 (excluding P33) and PC output sink current Ports P0 to P3 (excluding P33), P40 and P41 total sink current Ports P42, P43, P5, P6 and PC total sink current Ports P0 to P3 (excluding P33), P40 and P41 total source current Ports P42, P43, P5, P6 and PC total source current Power dissipation (DIP42S) Power dissipation (QIP48E) Operating temperature range Storage temperature range Symbol VDD VI1 VI2 VO1 VO2 -IOP1 -IOP2 ION ION1 ION2 -IOP1 -IOP2 PD1 PD2 Topr Tstg See note 3 See note 1 See note 2 See note 1 See note 2 Conditions Ratings -0.3 to +7.0 -0.3 to +15.0 -0.3 to VDD+0.3 -0.3 to +15.0 -0.3 to VDD+0.3 2 4 20 75 75 25 25 600 430 -30 to +70 -55 to +125 Unit V V V V V mA mA mA mA mA mA mA mW mW
C C
Notes 1. Open-drain output configuration option 2. All output configuration options 3. Heat-soak the QIP package before mounting. Do not immerse the package in the solder dip tank when mounting the QIP on the substrate, and avoid prolonged contact with the solder. Recommended Operating Conditions at Ta = 25C, VSS = 0V
Parameter Supply voltage Supply voltage range Hold-mode supply voltage range for data retention Symbol VDD VDD VDD Conditions Ratings 5 4.5 to 5.5 1.8 to 5.5 Unit V V V
Electrical Characteristics at Ta = -30 to +70C, VDD = 4.5 to 5.5V, VSS = 0V, unless otherwise noted
Parameter Symbol Conditions 4MHz ceramic resonator Reset-mode supply current IDD 4MHz external clock RC oscillator 4MHz ceramic resonator Halt-mode supply current IDDHT IDDHD VIL1 VIL2 VIL3 VIL4 VIM VIH1 VIH2 VIH3 VIH4 4MHz external clock RC oscillator Hold-mode supply current Ports P2, P3 (excluding P33), P5 and P6, RES and OSC1 LOW-level input voltage HOLD/P33 LOW-level input voltage Ports P0, P1, P4 PC, PD and PE, and TEST LOW-level input voltage Ports PE LOW-level input voltage Ports PE MID-level input voltage Ports P2 to P6 (excluding P33) HIGH-level input voltage HOLD/P33, RES and OSC1 HIGH-level input voltage Ports P0, P1, PC, PD and PE HIGH-level input voltage Port PE HIGH-level input voltage VDD=1.8 to 5.5V Output n-channel transistor OFF. See note 1. VDD=1.8 to 5.5V Output n-channel transistor OFF. See note 1. Ternary input mode. Ternary input mode. Output n-channel transistor OFF. See note 2. Output n-channel transistor OFF Output n-channel transistor OFF. See note 1. Ternary input mode. VSS VSS VSS VSS 0.4VDD
0.75VDD 0.75VDD
Ratings min ty p 4.5 6.5 4 3.0 3.5 3.0 0.01 max 8.0 11.0 8 5.0 6.0 5.0 10.0
0.25VDD 0.25VDD
Unit mA mA mA mA mA mA A V V V V V V V V V
0.3VDD 0.2VDD 0.6VDD 13.5 VDD VDD VDD
0.7VDD 0.8VDD
Continued on next page.
No.3122-4/15
LC66P308
Continued from preceding page.
Parameter Ports P0 to P6 (excluding P33) and PC LOW-level output voltage Ports P2, P3 (excluding P33), P6 and PC HIGH-level output voltage Ports P0, P1, P4 and P5 HIGH-level output voltage Ports PC and PD in-phase, comparator input voltage Port PD comparator offset voltage Ports P2, P3, P5 and P6, and RES and OSC1 Schmitt-trigger LOW-level threshold voltage Ports P2, P3, P5 and P6, and RES and OSC1 Schmitt-trigger HIGH-level threshold voltage Ports P2, P3, P5 and P6, RES and OSC1 Schmitt-trigger hysteresis voltage LOW-level input current for all inputs Ports P2 to P6 (excluding P33) HIGH-level input current Ports P0, P1 and P33, and RES and OSC1 HIGH-level input current Ports PC2, PC3, PD and PE HIGH-level input current Ports P2 to P6 output leakage current Ports P0, P1 and PC output leakage current Ports P0, P1, P4 and P5 output current with pull-up option Ceramic resonator input frequency Ceramic resonator input stabilization time RC oscillator input frequency External RC oscillator capacitance External RC oscillator resistance Symbol IOL=1.6mA IOL=10mA IOH=-1mA. See note 3. IOH=-0.1mA. See note 3. VDD=4.5V, IOH=-0.2mA. See note 4. IOH=-0.13mA. See note 4. VDD-1.0 VDD-0.5 2.4
VDD-1.35
Conditions
Ratings min typ max 0.4 1.5
Unit V V V V V V
VOL VOH1 VOH2 VCMM VOFF VtL
1.0 VI=1.0 to VDD-1.5V
0.25VDD
VDD-1.5 50 300 0.5VDD
V mV V
VtH VHYS IIL IIH1 IIH2 IIH3 IOFF1 IOFF2 IPO fCF fCFS fRC Cext Rext VI=VSS, output n-channel transistor OFF. See note 2 VI=13.5V, output n-channel transistor OFF. See note 2 VI=VDD. output n-channel transistor OFF. See note 1 VI=VDD, output n-channel transistor OFF. See note 1 VI=13.5V. See note 2. VI=VDD. See note 2. VI=VSS, VDD=5.5V. See note 4. 4MHz resonator 4MHz resonator R=2.2k1%, C=100pF5%
0.5VDD 0.1VDD -1
0.75VDD
V V A
5 1 1 5 1 -1.6 4 10 2 3 100 2.2 4
A A A A A mA MHz ms MHz pF k
Notes 1. Ports with CMOS output configuration option cannot be used as input ports. 2. Open-drain output configuration option 3. CMOS output configuration option 4. Pull-up output configuration option
No.3122-5/15
LC66P308
Timing Characteristics Serial input/output timing
Ta = -30 to +70 C, VDD = 4.5 to 5.5 V, VSS = 0V
Parameter Instruction cycle time SCK0 and SCK1 serial clock input cycle time SCK0 and SCK1 serial clock output cycle time SCK0 and SCK1 serial clock input pulsewidth SCK0 and SCK1 serial clock output pulsewidth SCK0 and SCK1 serial clock output rise time SCK0 and SCK1 serial clock output fall time SI0 and SI1 serial data setup time SI0 and SI1 serial data hold time SO0 and SO1 serial data output delay Symbol tCYC tCKCY tOCY tCKL tCKH tCKR tCKF tICK tCKI tCKO 0.3 0.3 0.3 Conditions Ratings min 0.92 0.9 2tCYC 0.4 tCYC 0.1 0.1 typ max 10 Unit s s s s s s s s s s
Note Each test input and output has an RC load as shown in the following figure.
External clock timing
Ta = -30 to +70 C, VDD = 4.5 to 5.5 V, VSS = 0V
Parameter OSC1 external clock input frequency OSC1 external clock LOW-level input pulsewidth OSC1 external clock HIGH-level input pulsewidth OSC1 external clock input rise time OSC1 external clock input fall time Symbol fext fextL fextH fextR fextF Conditions Ratings min 0.4 70 70 30 30 ty p max 4.35 Unit MHz ns ns ns ns
No.3122-6/15
LC66P308
Interrupt and reset timing
Ta = -30 to +70 C, VDD = 4.5 to 5.5 V, VSS = 0V
Parameter INT0 LOW-level pulsewidth INT0 HIGH-level pulsewidth INT1 and INT2 LOW-level pulsewidth INT1 and INT2 HIGH-level pulsewidth PIN1 LOW-level input pulsewidth PIN1 HIGH-level input pulsewidth RES LOW-level input pulsewidth RES HIGH-level input pulsewidth Symbol tIOL tIOH tI1L tI1H tPINL tPINH tRSL tRSH Conditions Ratings min 2tCYC 2tCYC 2tCYC 2tCYC 2tCYC 2tCYC 3tCYC 3tCYC typ max Unit s s s s s s s s
Comparator timing
Ta = -30 to +70 C, VDD = 4.5 to 5.5 V, VSS = 0V
Parameter Port PD comparator response time Symbol tRS Conditions Ratings min typ max 30 Unit s
No.3122-7/15
LC66P308
Input and Output Functions The LC66P308 has many multiplexed pins whose function is controlled by software. The function of each of these pins is shown in the following table.
Name D0/P00 D1/P01 D2/P02 D3/P03 D4/P10 D5/P11 D6/P12 D7/P13 A0/SI0/P20 A1/SO0/P21 A2/SCK0/P22 A3/INT0/P23 A4/INT1/P30 A5/POUT0/P31 A6/POUT1/P32 HOLD/P33 A7/P40 A8/P41 A9/P42 A10/P43 A11/P50 A12/P51 A13/P52 INT2/P53 SI1/P60 SO1/P61 SCK1/P62 DASEC/PIN1/P63 PC2/VREF0 PC3/VREF1 PD0/CMP0 PD1/CMP1 PD2/CMP2 PD3/CMP3/PGM PE0/TRA/CE PE1/TRB/OE OSC1 OSC2 RES VPP/TEST Ports PE0 to PE1 can be addressed as either a 2-bit pert or two, single-bit ports. They function as chip enable and write enable, respectively, when memory is addressed. They also function as three-level inputs. OSC1 and OSC2 function as the external ceramic resonator or RC oscillator oonnections. When an external clock is used, OSC2 is left open. When RES goes LOW while HOLD/P33 is HIGH, the CPU is reset. CPU test input. Normally connected to ground. PortS PD0 to PD3 can be addressed as either a 4-bit port or four, single-bit ports. They also function as comparator inputs. In addition, port PD3 also functions as the memory program control input. Ports PC2 and PC3 can be addressed as either a 2-bit port or two, single-bit ports. In addition, Port PC2 also functions as the PD0 reference voltage input, and PC3 as the PD1 to PD3 reference voltage input. Ports P60 to P63 can be addressed as either a 4-bit port or four, single-bit ports. Port P60 also functions as a serial data input, P61 as a serial data output, P62 as a serial data clock and P63 as a data security control input and timer 1 event counter input. Ports P50 to P53 can be addressed as either a 4-bit port, four, single-bit ports or an 8-bit port with P40 to P43. Ports P50 to P52 function as address bus inputs when memory is addressed. Port P53 also functions as an interrupt request input. Ports P40 to P43 can be addressed as either a 4-bit port, four, single-bit ports or an 8-bit port with P50 to P53. They function as address bus inputs when memory is addressed. Ports P30 to P32 can be addressed as either a 3-bit port, a 4-bit port with P33 or three, single-bit ports. They function as address bus inputs when memory is addressed. Port P30 also functions as an interrupt request input, P31 as a square-wave output from timer 0 and P32 as a square-wave output from timer 1 and a PWM output. Port P33 can be addressed as either a 4-bit port with P30 to P32 or a single-bit port. It functions as the hold-mode control input when P33 is LOW and the HOLD instruction is executed. The CPU restarts when P33 goes HIGH again. Reset signals are ignored whenever HOLD/P33 is LOW, including when not in hold mode. Ports P20 to P23 can be addressed as either a 4-bit port or four, single-bit ports. They function as address bus inputs when memory is addressed. Port P20 also functions as a serial data input, P21 as a serial data output, P22 as a serial data clock and P23 as an interrupt request, pulsewidth measurement and event counter input using timer 0. Ports P10 to P13 can be addressed as either a 4-bit port or four, single-bit ports. They function as data bus lines when memory is addressed. Level after reset is set by user option. Ports P00 to P03 can be addressed as either a 4-bit port or four, single-bit ports. They function as data bus lines when memory is addressed. They also have halt-mode control functions. Level after reset is set by user option. Function
No.3122-8/15
LC66P308
User Options Oscillator Options There are three user options for the oscillator-an external clock, an RC oscillator and a ceramic resonator. The internal circuits of OSC1 and OSC2 for the external clock, RC oscillator and ceramic resonator options are shown in figures 1, 2 and 3, respectively. Note the Schmitt-trigger inputs for both the external clock and RC oscillator options.
Figure 1. External clock option
Figure 2. RC oscillator option
Figure 3. Ceramic resonator option Output Options There are two user options for the output configuration of each port-n-channel open drain and p-channel, active pull-up, shown in figures 4 and 5, respectively. Ports P2, P3, P5 and P6 have Schmitt-trigger inputs in both output configurations. Figure 5. P-channel pull-up option The n-channel open-drain outputs for ports P2 to P6 have a withstand voltage greater than 15 V. Figure 4. N-channel open-drain option The p-channel pull-up option for ports P0, P1, P4 and P5 results in an n-channel sink transistor with a p-channel, active pull-up transistor configuration, and for ports P2, P3, P6 and PC, a CMOS configuration. Output Level After Reset Option The output level of ports P0 and P1 after a CPU reset is user selectable. Watchdog Timer Option A watchdog timer is available to prevent program runaway.
No.3122-9/15
LC66P308
PROM Specification Specifying Programs and Options The user-addressable memory is 0000H to 2007H. Addresses 0000H to 1FFFH are for user programs, and addresses 2000H to 2007H, for option specification.
Address Data bit D0 D1 D2 2000H D3 D4 D5 to D7 D0 D1 D2 2001H D3 D4 D5 D6 D7 D0 D1 D2 2002H D3 D4 D5 D6 D7 D0 D1 D2 2003H D3 D4 D5 D6 D7 D0 D1 2004H D2 D3 D4 to D7 2005H 2006H D0 to D7 D0 to D7 D0, D1 2007H D2 D3 D4 to D7 Watchdog timer function Port P0 level after reset Port P1 level after reset No function Oscillator No function Port P00 output configuration Port P01 output configuration Port P02 output configuration Port PO3 output configuration Port P10 output configuration Port P11 output configuration Port P12 output configuration Port P13 output configuration Port P20 output configuration Port P21 output configuration Port P22 output configuration Port P23 output configuration Port P30 output configuration Port P31 output configuration Port P32 output configuration No function Port P40 output configuration Port P41 output configuration Port P42 output configuration Port P43 output configuration Port P50 output configuration Port P51 output configuration Port P52 output configuration Port P53 output configuration Port P60 output configuration Port P61 output configuration Port P62 output configuration Port P63 output configuration No function No function No function No function Port PC2 output configuration Port PC3 output configuration No function Open-drain Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 CMOS Open-drain CMOS Open-drain Pull-up Open-drain Pull-up Set to 0 Open-drain CMOS Open-drain CMOS Open-drain Pull-up Open-drain Pull-up Parameter
Addresses 2008H and above can neither be programmed or read. The option specification is coded using the information shown in the following table.
Option 0 No LOW LOW Set to 0 RC oscillator or external clock Set to 0 Ceramic resonator 1 Ye s HIGH HIGH
The assembler execute command when specifying programs and options using a SANYO cross assembler is LC66S.EXE.
No.3122-10/15
LC66P308
PROM Programming The PROM can be programmed using a special adapter board, W66EP308D/408D for the 42-pin DIP and W66EP308Q/408Q for the 48-pin QIP as shown in the following figure, and a universal EPROM programmer.
Program the LC66P308 using the M mode of the PV command of the EVA800 or EVA850. The EPROM programmer should be Inte1 27128 compatible with VPP = 21 V. The recommended programmers are shown in the following table. Please contact your nearest SANYO representative if you intend to use an alternative EPROM programmer.
Manufacturer ADVANTEST SANYO Model TR4943, R4944A, R4945 or equivalent EVA850 or EVA800 special-purpose Programmers
The EPROM programmer adapter incorporates a data security switch. When this switch is ON, data is secure, and when OFF, the data lines are floating and the PROM can be programmed. Note that when the data lines are floating, the EPROM programmer will return an error. This error can be ignored.
Notes 1. Intel is a registered trademark of Intel Corporation. 2. ADVANTEST is a registered trademark of ADVANTEST Corporation.
No.3122-11/15
LC66P308
Application Notes Reset Timing The reset signal on RES should be held LOW for a minimum of three instruction cycles after the oscillator has
stabilized to ensure correct operation, as shown in the following figure.
After a reset occurs, all I/O ports are reset to open-drain output configuration with floating outputs, except for ports P0 and P1 which both have an output level after reset option. The output configuration of each port is then set using the specified options during the eight instruction cycles after RES goes HIGH. Program execution then begins from address 0000H. The LC66E308/P308 can be reset while in hold mode (HOLD/P33 is LOW). When RES goes LOW in hold mode, HOLD/P33 must go HIGH before RES goes HIGH again. Reference Clock The external circuit for a ceramic resonator is shown in figure 6, and the recommended resonator and component values, in the following table. The oscillator stabilization characteristics are shown in figure 7.
Ceramic resonator C1 4 MHz Murata CSA -4.00MG
Capacitance C2 33 pF 10% 33 pF 10% N/A
33 pF 10% 33 pF 10% N/A
4 MHz Kyocera KBR -4.0MS 4 MHz Murata CST -4.00MG with internal capacitor 4 MHz Kyocera KBR -4.OMES with internal capacitor
N/A
N/A
Figure 7. Ceramic resonator stabilization time
Figure 6. Ceramic resonator
No.3122-12/15
LC66P308
The external circuit for an RC oscillator is shown in the following figure. The RC oscillator frequency is determined by the external resistor and capacitor and has only been specified for Rext = 2.2 k and Cext = 100 pF. The frequency for other values of Rext and Cext can be determined from the graph in the following figure.
The external clock input connection is OSC1. The remaining oscillator connection, OSC2, should be left open as shown in the following figure.
Preparation Procedure The preparation procedures shown in the following figure for DIP and QIP packages should always be followed prior to mounting the packages on the substrate. Note that
the QIP package should be heat-soaked for 24 hours at 125 C immediately prior to mounting.
Screening procedure The construction of the microcontroller with a blank builtin PROM makes it impossible for SANYO to completely factory-test it before shipping. To prove reliability of the programmed devices, the screening procedure shown in the following figure should always be followed.
Note that it is not possible to perform a write test on the blank PROM. 100% yield, therefore, cannot be guaranteed.
No.3122-13/15
LC66P308
Ordering Information When ordering identical mask ROM and PROM devices simultaneously, provide an EPROM containing the target memory contents together with separate order forms for each of the mask ROM and PROM versions. When ordering a PROM device, provide an EPROM containing the target memory contents together with an order form. When ordering either an LC66354A 4 Kbyte or LC66356A 6 Kbyte mask ROM device, insert a jump command, or any similar command, to avoid executing an address beyond the range of the target device. In addition, write a 0 into all locations above 2007H. A comparison of the LC66P308 characteristics with those of the LC663XX mask ROM devices is shown in the following table.
LC663XX series Parameter Symbol Condition tCYC=0.92 to 10s Supply voltage range VDD tCYC=3.92 to 10s tCYC=1.96 to 10s 4MHz ceramic resonator Maximum halt-mode supply current IDDHT NHOLD fOSC=4MHz (tCYC=1s) Hold-mode release time tHOLD Cext Rext fOSC=2MHz (tCYC=2s) fOSC=1MHz (tCYC=4s) External RC oscillator capacitance External RC oscillator resistance Timer 0 contents after reset or hold-mode release Port output configuration after reset 4MHz external clock 3MHz (typ) RC oscillators Hold-mode release hardware delay LC66P308 4.5 to 5.5 - - 5.0 6.0 5.0 65,536 64 - - 100 2.2 FFO See note. LC6630X series 4.0 to 6.0 - - 2.5 3.5 2.5 65,536 64 - - 100 2.7 FFO Specified by user option LC66354A/6A/ 8A - 2.2 to 5.5 3.0 to 5.5 2.5 3.5 - 16,384 - 32 64 - - FFC Specified by user option pF k Hex ms Cycles mA V Unit
Note Ports P2 to P6 and PC are open-drain and floating. Ports P0 and P1 have pull-up resistances and are HIGH or LOW.
A breakdown of the LC66 series devices, which includes the LC66308 and LC663XX devices, is shown in the following table.
Device LC66304A/306A/308A LC66354A/356A/358A LC6635S/356S/358S LC66 E308 LC66 P308 LC66404A/406A/408A LC66 E408 LC66 P408 LC66506B/508B/512B/516B LC66556A/558A/562A/566A LC66E516 LC66P516 Pins 42/48 42/48 44 42/48 42/48 42/48 42/48 42/48 64 64 64 64 ROM capacity 4/6/8 Kbyte ROM 4/6/8 Kbyte ROM 4/6/8 Kbyte ROM 8 Kbyte EPROM 8 Kbyte PROM 4/6/8 Kbyte ROM 8 Kbyte EPROM 8 Kbyte PROM 6/8/12/16 Kbyte ROM 6/8/12/16 Kbyte ROM 16 Kbyte EPROM 16 Kbyte PROM RAM capacity 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes Package type DIP42S or QIP48E DIP42S or QIP48E QIP44M DIC42S or QIC48 DIP42S or QIP48E DIP42S or QIP48E DIC42S or QIC48 DIP42S or QIP48E DIP64S or QIP64A DIP64S or QIP64E DIC64S or QIC64 DIP64S or QIP64E
Note = under development SANYO ROM Services SANYO offers various services at nominal charges. These include ROM writing, ROM reading, and package stamping and screening. Contact your local SANYO representative for further information.
No.3122-14/15
LC66P308
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of June, 2001. Specifications and information herein are subject to change without notice.
PS No.3122-15/15

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Price & Availability of LC66P308

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